A semiconductor device typically includes a gate on a semiconductor substrate, spacers on sidewalls of the gate, and source and drain regions on opposed sides of the gate and in the semiconductor substrate. The width of the spacers determines the distance between the source and drain regions. Therefore, many functional device characteristics and parameters, such as the transistor saturation current, Isat, are highly dependent upon the spacer width. How to precisely produce the spacers having desired width becomes an important issue in the manufacturing process of the semiconductor device.
The spacers are conventionally produced by forming at least one dielectric layer over the gate, and performing an anisotropic dry etch process, so as to form the spacers along the sidewalls of the gate. Generally, etch time of the anisotropic dry etch process is determined by a thickness of the dielectric layer and a target spacer width. However, a variability of an actual width of the formed spacer between respective lots is still a problem needing to be addressed. Accordingly, there is a need for a method for accurately producing spacers with lower variability.